▎ 摘　　要

NOVELTY - A semi-floating gate memory comprises substrate, gate comprising graphene and formed on the substrate, metal contact electrode formed on the surface of the gate, barrier layer comprising a stack of perylenetetracarboxylic dianhydride layer/high dielectric constant material/perylenetetracarboxylic dianhydride layer and spaced apart from the metal contact electrode and formed on the surface of gate, semi-floating gate which is a two-dimensional material (M1) covering the barrier layer, two-dimensional material (M2) and tunneling layer are arranged in parallel on the surface of the semi-floating gate, channel layer which is two-dimensional material (M3), and source level and drain level are formed on the channel layer. The tunneling layer comprises a stack comprising perylenetetracarboxylic dianhydride layer (206), high dielectric constant material and perylenetetracarboxylic dianhydride layer. The materials (M2) and (M3) comprise heterojunction of high speed switch. USE - Semi-floating gate memory. ADVANTAGE - The semi-floating gate memory reduces leakage current and reduce power consumption using high dielectric constant materials as barrier layer and tunneling layer, and suppresses steric hindrance, increases nucleation density, inhibits leakage current and reduces power consumption using perylenetetracarboxylic dianhydride layer as buffer layer for growing high dielectric constant materials on the surface of two-dimensional materials. DETAILED DESCRIPTION - A semi-floating gate memory comprises substrate, gate comprising graphene and formed on the substrate, metal contact electrode formed on the surface of the gate, barrier layer comprising a stack of perylenetetracarboxylic dianhydride layer/high dielectric constant material/perylenetetracarboxylic dianhydride layer and spaced apart from the metal contact electrode and formed on the surface of graphene gate, semi-floating gate which is a two-dimensional material (M1) covering the barrier layer, two-dimensional material (M2) and tunneling layer are arranged in parallel on the surface of the semi-floating gate and is in contact with each other, channel layer which is two-dimensional material (M3) and covering the two-dimensional material (M2) and a tunneling layer, and source level and a drain level are formed on the channel layer. The tunneling layer comprises a stack comprising perylenetetracarboxylic dianhydride layer (206), high dielectric constant material and perylenetetracarboxylic dianhydride layer. The two-dimensional materials (M2) and (M3) comprise heterojunction of high speed switch. An INDEPENDENT CLAIM is included for preparation of the semi-floating gate memory.