• 专利标题:   Method for forming semiconductor device, involves configuring gate structure, source and drain components, semiconductor structure and two-dimensional material layer, and utilizing semiconductor structure and two-dimensional material layer as channels between source and drain components.
  • 专利号:   CN113707605-A, DE102021108344-A1, US2022045176-A1, KR2022018899-A, TW202207474-A
  • 发明人:   SHEN Z, KHADERBAD M A, MA H, SATHAIYA D M, ABHIJITH K M, SHEN T, DHANYAKUMAR S M
  • 专利权人:   TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MFG CO LTD
  • 国际专利分类:   H01L027/088, H01L021/8234, H01L021/285, H01L021/336, H01L029/778, H01L029/16, H01L029/24, H01L029/267, H01L029/66, H01L029/78, H01L029/06, H01L029/08, H01L029/10, H01L029/12, H01L029/423, H01L029/786, H01L021/60
  • 专利详细信息:   CN113707605-A 26 Nov 2021 H01L-021/8234 202204 Chinese
  • 申请详细信息:   CN113707605-A CN10901625 06 Aug 2021
  • 优先权号:   US062840P, US218212

▎ 摘  要

NOVELTY - The method involves providing workpieces (100) with semiconductor structures. A two-dimensional (2D) material layer is deposited on the semiconductor structure. A source component and a drain component electrically connected to the semiconductor structure and the two-dimensional material layer, are formed, in which the source component and the drain component comprise a semiconductor material. A gate structure is formed above the two-dimensional material layer, and the gate structure is placed between the source component and the drain component. The gate structure, the source component, the drain component, the semiconductor structure and the two-dimensional material layer are configured to form a field effect transistor. The semiconductor structure and the two-dimensional material layer are respectively utilized as a first channel and a second channel between the source component and the drain component. USE - Method for forming semiconductor device (claimed) e.g. FinFET, multi-bridge channel (MBC) transistors and multi-gate devices. ADVANTAGE - The method enables forming the semiconductor device in a simple and cost-effective manner. DESCRIPTION OF DRAWING(S) - Workpiece (100) Gate stack (110) Interface layer (112) High-k dielectric layer (114) Gate electrode (116)