▎ 摘　　要

NOVELTY - The memory has an SRAM memory cell and an interconnection wire structure (34) which are composed of two-dimensional semiconductor transistors, an address decoding circuit, a sensitive amplifier circuit, a control circuit and a driving/caching circuit. The two-dimensional semiconductor transistor comprises a channel formed by two-dimensional semiconductor materials, a grid electrode, a source electrode and a drain electrode. The transistor is conducted. Multiple SRAM memory cells form a memory cell array in a direction parallel to a substrate. Multiple memory cell arrays (31, 32, 33) form a multi-layer stack in a direction perpendicular to the substrate, interconnection within or between layers is realized by an interconnection wiring structure, and the plurality of SRAM memory cells are connected to an address decoding circuit, a sense amplifier circuit, a control circuit, and a driving/buffer circuit in a memory. USE - High density SRAM used in integrated circuit chip. ADVANTAGE - Improves the storage density and reduces the cost on the premise of ensuring the performance of the static random access memory since the storage unit can be stacked in multiple layers in a direction perpendicular to the substrate, and the connection between the layers or layers is realized by the interconnection wire structure. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram of the high density SRAM. Memory cell arrays (31,32,33) Interconnection wire structure (34)