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  • 专利标题:   Tunneling FET unit, has first dielectric layer arranged in graphite layer, insulating barrier layer provided with second dielectric layer that is arranged in top gate electrode, where gate electrode is connected to graphene nanometer belt.
  • 专利号:   CN103400859-A, CN103400859-B
  • 发明人:   WANG H, XIE X, TANG S, WU T, XIE H, LIU X, SONG Y, SUN Q
  • 专利权人:   SHANGHAI INST MICROSYSTEM INFORMATION
  • 国际专利分类:   H01L021/28, H01L021/336, H01L029/49, H01L029/78
  • 专利详细信息:   CN103400859-A 20 Nov 2013 H01L-029/78 201406 Pages: 16 Chinese
  • 申请详细信息:   CN103400859-A CN10352264 13 Aug 2013
  • 优先权号:   CN10352264

▎ 摘　　要

NOVELTY - The FET unit has a substrate provided with a bottom gate electrode. A first dielectric layer is arranged in a graphite layer. An insulating barrier layer is provided with a second dielectric layer that is arranged in a top gate electrode. The top gate electrode is connected with a graphene nanometer belt. The insulating barrier layer is provided with a hexagonal boron nitride film. Thickness of a disulfide key thin film is 2nm. A gate electrode contact part is connected with the top gate electrode. USE - Tunneling FET unit. ADVANTAGE - The FET unit improves high voltage switch of the top gate electrode precision in a convenient manner. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are also included for the following: (1) a graphene array for a tunneling FET unit (2) a tunneling FET unit Graphene array forming method. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of a tunneling FET unit.