• 专利标题:   Multi-layer graphene double-grid FET for use in high frequency large power device, has transistor unit formed with multiple layers, where source and drain electrodes of transistor unit are connected together in parallel manner.
  • 专利号:   CN103208524-A, CN103208524-B
  • 发明人:   GUO C, MA Z, ZHANG P, WU Y, ZHUANG Y, XIAO Z, FENG Y, ZHAO Y
  • 专利权人:   UNIV XIDIAN
  • 国际专利分类:   H01L021/336, H01L029/78
  • 专利详细信息:   CN103208524-A 17 Jul 2013 H01L-029/78 201373 Pages: 7 Chinese
  • 申请详细信息:   CN103208524-A CN10148699 25 Apr 2013
  • 优先权号:   CN10148699

▎ 摘  要

NOVELTY - The FET has a transistor unit whose rear gate metal electrode is arranged on a substrate, where the substrate is made of hexagonal-boron nitride (h-BN) material i.e. two-dimensional plane material. A rear gate dielectric layer is formed on the rear gate metal electrode. A graphene single layer is matched with the rear gate dielectric layer and a top gate metal electrode. The transistor unit is formed with multiple layers in parallel manner. A source electrode and a drain electrode of the transistor unit are connected together in parallel manner. USE - Multi-layer graphene double-grid FET for use in a high frequency large power device. ADVANTAGE - The FET has wide range of applications, and utilizes hexagonal-boron nitride as top gate and bottom gate media- so as to improve graphene channel carrier mobility and limit graphene FET drain-source current. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a multi-layer graphene double-grid FET preparing method. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional view of a multi-layer graphene double-grid FET. '(Drawing includes non-English language text)'