▎ 摘　　要

NOVELTY - The manufacturing method involves forming the passivation oxide layer on the upper portion of the silicon transistor (S100). The through-hole passing through the passivation oxide layer is formed (S200) using lithography and etching process in the electrode of the silicon transistor. A metallic layer is formed (S300) in the upper portion of the silicon transistor and the through-hole. The silicon transistor and graphene device are connected (S400) using the metallic layer. A graphene device is formed in the predetermined portion of the single layer grown up to the chemical vapor deposition (CVD) or the oxide graphene. The oxide layer of the multi layer in silicone is evaporated. The predetermined portion of the upper unit of silicon wafer is exposed. The arsenic is injected into the P-well domain. The second oxide layer is silicon nitride layer, and oxide graphene. USE - Manufacturing method for the graphene-silicone fusion electric circuit element (Claimed). ADVANTAGE - The graphene device is formed in the predetermined portion of the single layer grown up to the chemical vapor deposition or the oxide graphene, and hence enhances the efficiency of the circuit element. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a graphene-silicone fusion electric circuit element. DESCRIPTION OF DRAWING(S) - The drawing shows a flow chart of the manufacturing method. (Drawing includes non-English language text). Forming the field oxide at the upper unit of the silicon wafer (S30) Forming the passivation oxide layer on the upper portion of the silicon transistor (S100) Forming the through-hole passing through the passivation oxide layer (S200) Forming the metallic layer in the upper portion of the silicon transistor and the through-hole (S300) Connecting the silicon transistor and graphene device (S400)