▎ 摘　　要

NOVELTY - Classifier circuit comprises: an array of dual gate graphene transistors, where each of the transistors has a source, a top gate receiving one of an input voltage to be evaluated or a reference voltage, a bottom or embedded gate receiving the other of the input voltage or reference voltage and a drain, the source and drain contacting a graphene channel, and one of the source and the drain is connected to a voltage source; and a common output combining output current of many dual gate graphene transistors, the output current that varying in response to the difference between the input voltage and the reference voltage. USE - The classifier circuit is useful for forming a graphene classifier transistor (claimed). ADVANTAGE - The classifier circuit forms classifier transistor with high remanent polarization forms dielectric with ferroelectric capability on a low resistivity substrate. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for forming a graphene classifier transistor, comprising forming dielectric with ferroelectric capability on a low resistivity substrate (112), forming a non-ferroelectric oxide layer on the dielectric, forming a recess window in the non-ferroelectric oxide layer, transferring graphene into the recess window, patterning a graphene channel using lithography and etching, forming source/drain contacts on graphene channel, depositing top gate dielectric on graphene channel, and forming a top gate electrode on the top gate dielectric layer. DESCRIPTION OF DRAWING(S) - The figure shows cross-sectional view of graphene ferroelectric transistor, which consists of local embedded-gate and non-ferroelectric gate dielectrics. Graphene ferroelectric transistor (100) Substrate (112) Bottom gate dielectric layer (118) Source terminal (122) Drain terminal (124)