▎ 摘　　要

NOVELTY - The method involves forming a conductive interconnect portion in a first dielectric layer. A second dielectric layer is formed on the first dielectric layer. Another conductive interconnect portion is formed in the second dielectric layer. A graphene layer is formed on the second dielectric layer. A source region (104) is formed on the second dielectric layer, and a drain region (106) is formed on the second dielectric layer. A third dielectric layer is formed on the graphene layer. Metallic gate material is formed on the third dielectric layer. USE - Method for forming a 3-D integrated circuit (claimed) i.e. hybrid integrated circuit. ADVANTAGE - The method enables forming silicon FET devices and graphene devices on a wafer in the integrated circuit to offer increased performance benefits. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a three dimensional (3-D) integrated circuit comprising a silicon substrate. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a portion of a 3-D hybrid integrated circuit including a topgated graphene FET. 3-D hybrid integrated circuit (100) Silicon FET device (101) Silicon wafer substrate (102) Top-gated graphene FET device (103) Source region (104) Drain region (106)