▎ 摘　　要

NOVELTY - The device has a channel layer (6a) is provided on the upper surface of the drift zone (4). A passivation layer (6b) is provided on the bottom surface of the channel layer. A portion of the drift region and portion of the channel layer, passivation layer and composite pillars are delimited as a cell region (9). The other portion of the drift region and portion of the channel layer, passivation layer and composite pillars are designated as terminal regions (10). A dielectric layer (6c) is provided on the surface of the passivation layer in the cell region and the outside of the channel layer. A gate metal electrode (7) is provided on the outside of the dielectric layer. A heavily doped semiconductor layer (5c) is provided on the top surface of the channel layer in the cell region. A source metal electrode (8) is provided on the heavily doped semiconductor layer. The channel layer in the terminal region is extended and wrapped by the passivation layer in the terminal region. USE - High-threshold power semiconductor device. ADVANTAGE - The threshold voltage of the device is increased, the blocking characteristics of the device is improved, and the gate capacitance is reduced. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a manufacturing method of high threshold power semiconductor device. DESCRIPTION OF DRAWING(S) - The drawing shows a perspective view of the high-threshold power semiconductor device. Drift zone (4) Heavily doped semiconductor layer (5c) Channel layer (6a) Passivation layer (6b) Dielectric layer (6c) Gate metal electrode (7) Source metal electrode (8) Cell region (9) Terminal region (10)