• 专利标题:   Method for modifying walls and bottoms of holes with reduced graphene oxide, involves providing substrate with copper cladding layer and drilled holes, while modifying walls and bottoms of holes with reduced graphene oxide.
  • 专利号:   US2018310414-A1, TW201839180-A, US10306768-B2
  • 发明人:   YEH A, YANG N, YEH D, YANG F
  • 专利权人:   YEH A, TRIALLIAN CORP, YEH D, TRIALLIAN CORP, YEH A
  • 国际专利分类:   H05K001/11, H05K003/06, H05K003/42, C25D005/34, C25D007/06, H05K003/18, H05K003/00, H05K001/09, H05K003/26, H01L021/48, H01L023/498, H05K003/40
  • 专利详细信息:   US2018310414-A1 25 Oct 2018 H05K-003/06 201877 Pages: 8 English
  • 申请详细信息:   US2018310414-A1 US876140 20 Jan 2018
  • 优先权号:   TW113528

▎ 摘  要

NOVELTY - The method involves providing a substrate with a copper cladding layer and drilled holes. The walls and bottom of the holes are modified with reduced graphene oxide. The holes are filled with copper, and a thin flat copper layer (20) is formed over the copper cladding layer. A patterned anti-plating film is formed on the thin flat copper layer to define an area of traces having the width of 3-50 micrometer. The copper is deposited on the area of traces with thicknesses of 5-50 micrometer at a variation of less than fifteen percent through a periodic pulse reverse plating process. The anti-plating film is removed, and the thin flat copper layer and copper cladding layer is etched without depositing the copper. USE - Method for modifying walls and bottoms of the holes with reduced graphene oxide. ADVANTAGE - The fine traces possess superior shapes. The thin flat copper layer is quickly removed without undercut. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a printed circuit board comprises a non-conductive substrate with drilled holes. DESCRIPTION OF DRAWING(S) - The drawing shows a sectional schematic view of a blind vias. Copper layer (20) Non-conducting substrate (30) Via (40)