• 专利标题:   Method for fabricating integrated circuit chip utilized in e.g. computer product, involves forming dielectric layer on graphene channel with molecular beam deposition process, and forming gate contact over graphene channel and on dielectric.
  • 专利号:   US2014113416-A1
  • 发明人:   BOJARCZUK N A, COPEL M W, LIN Y
  • 专利权人:   INT BUSINESS MACHINES CORP
  • 国际专利分类:   H01L021/02, H01L029/66
  • 专利详细信息:   US2014113416-A1 24 Apr 2014 H01L-029/66 201431 Pages: 14 English
  • 申请详细信息:   US2014113416-A1 US536875 28 Jun 2012
  • 优先权号:   US536875

▎ 摘  要

NOVELTY - The method involves providing a substrate (504). Source and drain contacts (908) are formed on the substrate. A graphene channel is formed on the substrate connecting the source contact and the drain contact. A dielectric layer is formed on the graphene channel with a molecular beam deposition process. A gate contact (1716) is formed over the graphene channel and on the dielectric, where the gate contact is in a non-overlapping position with the source and drain contacts leaving exposed sections (1918) of the graphene channel between the gate contact and the source and drain contacts. USE - Method for fabricating a carbon-based semiconductor device e.g. graphene channel based nano-device such as integrated circuit chip, utilized in an end product e.g. toy and computer product. ADVANTAGE - The method allows carriers to easily escape through a dielectric by tunneling when either a valence or conduction band lies close to a Dirac point so as to provide a reliable and scalable technique to deposit uniform high-k dielectric layers on the graphene channel without use of seed layers to improve capacitance of the device, while inducing minimal impact to transport in the graphene channel at the same time, thus allowing a sample to be kept at low temperatures during deposition and providing dangling bonds to nucleate growth of the insulating layer, and hence hindering mobility of adsorbed species and obtaining high performance devices. DETAILED DESCRIPTION - The substrate is a silicon carbide wafer. DESCRIPTION OF DRAWING(S) - The drawing shows a top perspective view of portions of a gate dielectric not covered by a gate metal contact that is etched away. Substrate (504) Source and drain contacts (908) Gate contact (1716) Exposed sections (1918)