▎ 摘　　要

NOVELTY - The method involves patterning layers of materials and a layer of metal to form source and drain regions spaced apart, where respective regions comprise a portion on the patterned metal and a portion on an insulating substrate (16). The layer of material is heated on the patterned metal to cause reaction for forming reacted region of one of a chemical compound and an alloy. Un-reacted patterned metal is selectively removed to expose a patterned carbon-based nanostructure layer (116) between the source region and the drain region. USE - Method for forming a device structure e.g. carbon nano-tube device structure and graphene device structure. ADVANTAGE - The method enables maintaining a carbon nano-tube or graphene from being exposed to undesirable organic moieties to be presented during resist processing steps. The method enables utilizing dielectric layer functions to provide additional dielectric spacing to space source and drain from a gate electrode, thus reducing source and drain capacitance to the gate electrode. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-section view of a double gate FET with a lower gate dielectric patterned to cover a bottom gate electrode. Insulating substrate (16) Patterned carbon-based nanostructure layer (116) Embedded bottom gate (240) Bottom gate dielectric (244) Source (248) Channel-protect residuals (252, 254)