▎ 摘　　要

NOVELTY - The apparatus has multiple sets of NAND strings and each NAND string has memory cells (400,410,420) with a control gate (402,412,422) and drain select gates. Multiple bit lines are associated with the sets of strings. Multiple managing circuits are connected to the strings and to the bit lines. The managing circuits apply voltages to multiple bit lines in accordance with a data pattern. The circuits apply a select voltage to the gates and concurrently apply a program pulse to control gates of a different set of selected memory cells in each respective set of the strings while the select voltage is applied to the drain gates. USE - Apparatus for concurrently programming multiple storage cells of non-volatile memory elements. Uses include but are not limited to ReRAM, Memristor memory, programmable metallization cell memory, phase-change memory, PCM, PCME, PRAM, PCRAM, ovonic unified memory, chalcogenide RAM, or C-RAM, NAND Flash (RTM: Computer multimedia application) memory such as 2D NOT AND (2D NAND) Flash (RTM: Computer multimedia application) memory, 3D NOT OFF (3D NOT OR (3T NAND), NOR Flash (RTM: Computer multimedia application) memory (nano RAM or NRAM), nanocrystal wire-based memory, silicon-oxide based sub-10 nanometer process memory, graphene memory, SONOS, ADVANTAGE - The memory die comprises a set of non-volatile storage cells arranged into a first block having a first string of storage cells that intersects with a first word line at a first storage cell and a second block including a second string, where bit line is electrically connectable to the first string and the second string and a controller is configured to concurrently apply a programming pulse to the word lines to concurrently program the first and second storage cells to a common target threshold voltage, and thus enables to allow recovery of a stored data value. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are included for the following: 1.a method for concurrently programming multiple storage cells of non-volatile memory storage device; and 2.a system for concurrently programming multiple storage cells of non-volatile memory storage device. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of charge-trapping memory cells in NAND strings. Memory cells (400,410,420) Control gate (402,412,422) Channel region (406) Tunneling region (409) Charge-trapping layer (414)