• 专利标题:   Preparation of nanofluidic chip used for e.g. virus detection, involves anodic aligning and bonding silicon wafer after processing graphene nanochannel, and glass after placing graphene to obtain nanofluidic chip, through alignment marks.
  • 专利号:   CN114534815-A, CN114534815-B
  • 发明人:   MA M, CUI G
  • 专利权人:   UNIV TSINGHUA
  • 国际专利分类:   B01L003/00, B81C001/00, B81C003/00
  • 专利详细信息:   CN114534815-A 27 May 2022 B01L-003/00 202261 Chinese
  • 申请详细信息:   CN114534815-A CN10435273 24 Apr 2022
  • 优先权号:   CN10435273

▎ 摘  要

NOVELTY - The method involves etching microfluidic channel and first alignment mark on silicon wafer, and making second alignment mark on BF33 glass. The microchannel and the silicon wafer are cleaned and etched after the first alignment mark and making the BF33 glass after the second alignment mark. The graphene sample is transferred to the designated position of the cleaned silicon wafer and BF33 glass. The graphene nanochannels are processed on the silicon wafer by AFM. The silicon wafer after processing the graphene nanochannel, and the BF33 glass after placing the graphene are anodic aligned and bonded to obtain a nanofluidic chip, through the first alignment mark and the second alignment mark. USE - Preparation method of nanofluidic chip (claimed) based on AFM scribed graphene, used for virus e.g. coronavirus and biological macromolecule detection, nano-drug development and precise medical treatment. ADVANTAGE - The method has processing high precision, simple operation, high compatibility, large design space, and provides the nano-channel with high length-diameter ratio, continuously and accurately controllable channel size in the range of nanometer to dozens of nanometers, good sealing performance, and smooth inner wall of hydrophobic, uniform structure and property with excellent electrical, thermology, mechanical property and chemical stability. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a nanofluidic chip based on atomic force microscopy (AFM) scribed graphene. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram of the silicon wafer design layout. (Drawing includes non-English language text)