• 专利标题:   Method for preparing graphene field effect transistor, involves providing insulating substrate, forming graphene conductive layer, depositing gate dielectric layer followed by etching gate dielectric layer and forming source electrode.
  • 专利号:   CN105789032-A, CN105789032-B
  • 发明人:   JIN Z, PENG S, ZHANG D, WANG S, SHI J, MAO D
  • 专利权人:   INST MICROELECTRONICS CHINESE ACAD SCI, INST MICROELECTRONICS CHINESE ACAD SCI
  • 国际专利分类:   H01L021/04, H01L029/16, H01L029/786
  • 专利详细信息:   CN105789032-A 20 Jul 2016 H01L-021/04 201658 Pages: 10 Chinese
  • 申请详细信息:   CN105789032-A CN10306272 10 May 2016
  • 优先权号:   CN10306272

▎ 摘  要

NOVELTY - A graphene field effect transistor preparing method involves providing an insulating substrate, forming graphene conductive layer on the insulating substrate, depositing a gate dielectric layer, forming a gate electrode. The gate electrode with the gate sidewall spacer is utilized as a mask, the gate dielectric layer is etched followed by forming the device, forming a source electrode and a drain electrode, self-aligning with the gate electrode structure, etching the gate sidewall, so that the gate electrode and the source electrode structure of an air gap is formed between the electrode. USE - Method for preparing graphene field effect transistor. ADVANTAGE - The method enables reducing the passage area of ??the device, reducing the parasitic resistance by the sidewall etching, reducing the gate-source, gate-drain parasitic capacitance, and improving the performance of graphene RF field effect transistor. DETAILED DESCRIPTION - A graphene field effect transistor preparing method involves providing an insulating substrate, forming graphene conductive layer on the insulating substrate, depositing a gate dielectric layer on the conductive layer, forming a gate electrode on the gate dielectric layer, depositing gate sidewall spacer film on the device, performing maskless anisotropic etching, forming gate sidewall spacer on both sides of the gate electrode, exposing gate electrode and regions other than the gate sidewall spacer gate dielectric layer. The gate electrode with the gate sidewall spacer is utilized as a mask, the gate dielectric layer is etched to remove the electrode not covered with the gate dielectric gate, followed by forming the device on the metal layer, forming a source electrode and a drain electrode, self-aligning with the gate electrode structure, etching the gate sidewall, so that the gate electrode and the source electrode structure of an air gap is formed between the gate electrode and a drain electrode. An INDEPENDENT CLAIM is also included for a graphene field effect transistor prepared by the method.