▎ 摘　　要

NOVELTY - A memory device (20) comprises first semiconductor die (510) and memory cube (PU) which is mounted on and connected with first semiconductor die and includes multiple stacked tiers (10A, 10B, 10C, 10D). Each tier includes second semiconductor dies (110, 210, 310, 410) laterally wrapped by an encapsulant (130, 230, 330, 430) and redistribution structures (140, 240, 340, 440) placed on second semiconductor dies and encapsulant. Second semiconductor dies are electrically connected with first semiconductor die through the redistribution structures in the multiple stacked tiers, where each redistribution structure includes redistribution patterns. Redistribution structure closest to first semiconductor die further has a thermally conductive layer connected to first semiconductor die. Material of redistribution patterns is different from material of thermally conductive layer. Thermally conductive layer is electrically isolated from first and second semiconductor dies. USE - A memory device. ADVANTAGE - By disposing the thermally conductive layer electrically isolated from the semiconductor dies in the bottommost tier, the heat dissipation efficiency of the memory device is greatly increased. As a result, the reliability of the memory device is enhanced, and the performance of the memory device is boosted. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for manufacture of memory device which involves forming first redistribution patterns in a first dielectric layer; forming second redistribution patterns electrically connected with first redistribution patterns on first dielectric layer with a first material; forming a thermally conductive layer electrically isolated from first redistribution patterns and second redistribution patterns over the first dielectric layer with a second material different form the first material; and forming a second dielectric layer over the first dielectric layer, where second redistribution patterns and thermally conductive layer are embedded in the second dielectric layer. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional diagram a manufactured memory device. 20Memory device 510First semiconductor die 10A,10B,10C,10DMultiple stacked tiers 110,210,310,410Second semiconductor dies 130,230,330,430Encapsulant 140,240,340,440Redistribution structures