• 专利标题:   Semiconductor device with favorable contact between wiring structure and graphene layer, has gate electrode formed on gate insulating film which is formed on third area between first area and second area of graphene layer.
  • 专利号:   JP2012060010-A, JP5671896-B2
  • 发明人:   NIHEI M, SATO M
  • 专利权人:   FUJITSU LTD, FUJITSU LTD
  • 国际专利分类:   H01L021/28, H01L021/3205, H01L021/336, H01L023/52, H01L029/417, H01L029/786, H01L021/768, H01L023/532
  • 专利详细信息:   JP2012060010-A 22 Mar 2012 H01L-021/28 201222 Pages: 16 Japanese
  • 申请详细信息:   JP2012060010-A JP203293 10 Sep 2010
  • 优先权号:   JP203293

▎ 摘  要

NOVELTY - The semiconductor device has a first wiring portion (20) formed in the first area of a graphene layer (14), and a second wiring portion (22) formed in the second area of the graphene layer. The first wiring portion has a first network nano graphite layer laminated on the graphene layer. The second wiring portion has a second network nano graphite layer laminated on the graphene layer. A gate insulating film (28) is formed on the third area between the first area and second area of the graphene layer. A gate electrode (32) is formed on the gate insulating film. USE - Semiconductor device with favorable contact between wiring structure and graphene layer. ADVANTAGE - Ensures reduced contact resistance in the graphene layer of the channel of the semiconductor device since the wiring part of the semiconductor device forms a network nano graphite layer on a graphene layer continuously from the channel part. Ensures small power consumption due to low electrical resistance in the surface direction and vertical direction of the wiring structure in the semiconductor device. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for the semiconductor device manufacture method. DESCRIPTION OF DRAWING(S) - The drawing is a perspective view showing the structure of the semiconductor device. Graphene layer (14) First wiring portion (20) Second wiring portion (22) Gate insulating film (28) Gate electrode (32)