▎ 摘　　要

NOVELTY - The method involves forming silicon oxide layer on a substrate (10). A contact metal (19) is provided in a region to form source and drain at the bottom of silicon oxide layer. A graphene channel layer (16) is formed on silicon oxide layer. The graphene trench layer is provided to form source drain metal contact area. The silicon oxide layer is removed from source end and drain end. The cavity (18) is formed below graphene channel layer. The grid structure is formed between source and drain ends of trench layer. A wet etching is performed using hydrofluoric acid, ammonium fluoride. USE - Method for manufacturing FET (claimed). ADVANTAGE - The channel region resistivity can be reduced, such that the prepared graphene FET is provided with a smaller source/drain contact resistance. The excellent stability of the FET can be achieved. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a FET. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of the FET. Substrate (10) Gate electrode layer (15) Graphene channel layer (16) Cavity (18) Contact metal (19)