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  • 专利标题:   Vertical transistor device comprises a channel region comprising least one layer of two-dimensional (2D) material, bottom source/drain region, top source/drain region, and gate structure positioned all around one layer.
  • 专利号:   US2021242094-A1, US11177182-B2
  • 发明人:   CIMINO S, STREHLOW E, PRABHU M, NAYYAR N, REN H, SUN K, PRITCHARD D, YANG H
  • 专利权人:   GLOBALFOUNDRIES US INC
  • 国际专利分类:   H01L021/8238, H01L029/66
  • 专利详细信息:   US2021242094-A1 05 Aug 2021 H01L-021/8238 202179 English
  • 申请详细信息:   US2021242094-A1 US776636 30 Jan 2020
  • 优先权号:   US776636

▎ 摘　　要

NOVELTY - Vertical transistor device comprises a channel region comprising at least one layer of a two-dimensional (2D) material, a bottom source/drain region, a top source/drain region, and a gate structure positioned all around one layer of a two-dimensional (2D) material. USE - Vertical transistor device. ADVANTAGE - The vertical transistor device has beneficial properties, such as high mechanical strength, high electronic and thermal conductivity, and/or unique quantum-mechanical effects. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method of manufacturing vertical transistor device.