▎ 摘　　要

NOVELTY - The utility model claims display technology area, and claims a kind of low temperature polycrystalline silicon thin film transistor, array substrate and display panel. The low temperature polycrystalline silicon thin film transistor comprises: including set up on substrate of the active region layer, source electrode, drain electrode, grid electrode, the active region layer and the grid insulation layer, and is set with the oxidation graphene in between the active region layer and the grid insulation layer between the grid electrode. By oxidation graphene formed in between active region layer and grid insulation layer, reduce polysilicon between active region layer and grid insulation layer surface roughness and surface defect state density, and no need for gate insulation layer prevention cleaning process. Also claims of including array placode and displaying panel and the polycrystalline silicon thin film transistor.