▎ 摘　　要

NOVELTY - The graphene-based field effect transistor comprises a graphene layer (20) located on an insulating layer, a first metal portion (50), a second metal portion (60), a first electrode, a second electrode, a gate dielectric layer (40), a dielectric seed layer (30), a gate electrode, a contact level dielectric material layer, a first contact via structure, and a second contact via structure. The first metal portion overlies on a portion of the graphene layer, and contacts an upper surface of the gate dielectric layer. The second metal portion contacts and overhangs the first metal portion. USE - The graphene-based field effect transistor is useful for high-frequency electronics. ADVANTAGE - The graphene-based field effect transistor can be economically manufactured with improved performance, minimized access resistance and excellent conductivity. DETAILED DESCRIPTION - The graphene-based field effect transistor comprises a graphene layer (20) located on an insulating layer, a first metal portion (50), a second metal portion (60), a first electrode, a second electrode, a gate dielectric layer (40), a dielectric seed layer (30), a gate electrode, a contact level dielectric material layer, a first contact via structure, and a second contact via structure. The first metal portion overlies on a portion of the graphene layer, and contacts an upper surface of the gate dielectric layer. The second metal portion contacts and overhangs the first metal portion. The first electrode contacts the portion of the graphene layer, and is laterally offset from a first sidewall of the first metal portion by a lateral spacing. The second electrode contacts another portion of the graphene layer, and is laterally offset from a second sidewall of the first metal portion by the lateral spacing. The gate dielectric layer strads over the portion of the graphene layer, and includes a dielectric metal oxide having a dielectric constant of greater than 4.0. The dielectric seed layer contacts a top surface of the portion of the graphene layer and a bottom surface of the gate dielectric layer, and includes an adsorbed monolayer of nitrogen dioxide, a polymer layer and a dielectric oxidized metal having an atomically non-uniform thickness. The lateral spacing is same as a lateral overhang distance of the second metal portion placed over the first metal portion. The overhang distance is constant around an entirety of sidewalls of the first metal portion. The gate electrode contacts a top surface of the second portion, and is embedded in the contact level dielectric layer. The first electrode, second electrode and gate electrode have a same thickness and a same composition of a conductive material. The contact level dielectric material layer contacts the first metal portion and the first and second electrodes and the top surface of the graphene layer at the portions. An area of contact at each of the portions has a constant width that is same as the lateral spacing. The first and second contact via structures contact the first and second electrodes respectively, and are embedded in the contact level dielectric layer. An INDEPENDENT CLAIM is included for a method of forming a transistor structure. DESCRIPTION OF DRAWING(S) - The diagram shows a schematic vertical cross-sectional view of a transistor structure. Graphene layer (20) Dielectric seed layer (30) Gate dielectric layer (40) First metal portion (50) Second metal portion. (60)