• 专利标题:   Resistive memory device comprises word lines laterally extends along second horizontal direction and laterally spaced apart along first horizontal direction, and selector material layer located between each of word lines.
  • 专利号:   US2021184111-A1, CN112992858-A, TW202125714-A, US11349069-B2
  • 发明人:   LI L, CHEN T, CHENG C, CHIANG H, JIANG H, ZHENG Z, CHEN Z
  • 专利权人:   TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MFG CO LTD
  • 国际专利分类:   H01L027/24, H01L045/00, H01L023/532, G11C013/00, H01L021/76, H01L021/8239
  • 专利详细信息:   US2021184111-A1 17 Jun 2021 H01L-045/00 202153 English
  • 申请详细信息:   US2021184111-A1 US715216 16 Dec 2019
  • 优先权号:   US715216

▎ 摘  要

NOVELTY - Resistive memory device comprises array of rail structures that extend along first horizontal direction. The rail structures comprises bit line. The word lines laterally extends along second horizontal direction and are laterally spaced apart along first horizontal direction. The word lines comprises respective horizontally-extending portion that overlie rail structures. The respective row of downward-protruding portions protrudes downward from respective horizontally-extending portion. The layer stack of resistive memory material layer and selector material layer is located between each of word lines and respective underlying portions of array of rail structures. The word lines or subset of bit lines comprises carbon-based conductive material containing hybridized carbon atoms in hexagonal arrangement. USE - Resistive memory device. ADVANTAGE - The resistive memory device increases thickness. DETAILED DESCRIPTION - INDEPENDENT CLAIMS are included for the following: 1. a memory device, which comprises resistive memory array located over substrate, where resistive memory array comprises vertical stacks of respective lower bit line, respective inter-bit-line dielectric rail, and respective upper bit line. 2. a method for forming resistive memory array over substrate, which involves: a. forming array of rail structures that extend along first horizontal direction over substrate, where rail structures comprises bit line; b. forming dielectric isolation structures extending along second horizontal direction over array of rail structures, where sidewalls of rail structures are physically exposed to line trenches located between neighboring pairs of dielectric isolation structures; c. forming layer stack of resistive memory material layer and selector material layer within each of line trenches; d. forming word line on each of layer stacks within unfilled volumes of line trenches, where word lines or subset of bit lines comprise carbon-based conductive material containing hybridized carbon atoms in hexagonal arrangement. DESCRIPTION OF DRAWING(S) - The drawing shows vertical cross-sectional view of resistive memory device. Substrate (8) Semiconductor material layer (10) Shallow trench isolation structures (12) Gate structures (20) Gate dielectric (22)