• 专利标题:   Semiconductor device, has foundation layer including first and second layers, catalyst layer formed on surface of foundation layer, where catalyst layer includes protruding area, and graphene layer is in contact with protruding area.
  • 专利号:   US2016056256-A1, JP2016046324-A, US9484206-B2, JP6246676-B2
  • 发明人:   ISHIKURA T, KAJITA A, SAKAI T, ISOBAYASHI A, WADA M, SAITO T, KITAMURA M, SAKATA A
  • 专利权人:   TOSHIBA KK, TOSHIBA KK
  • 国际专利分类:   H01L021/283, H01L023/544, H01L029/45, H01L021/28, H01L021/285, H01L021/3205, H01L021/768, H01L023/532, H01L021/02, H01L023/48, H01L029/16
  • 专利详细信息:   US2016056256-A1 25 Feb 2016 H01L-029/45 201619 Pages: 21 English
  • 申请详细信息:   US2016056256-A1 US637041 03 Mar 2015
  • 优先权号:   JP167886

▎ 摘  要

NOVELTY - The device has a foundation layer including first and second layers being different from each other in material, where the foundation layer includes a surface on which boundary of the first and second layers is presented. A catalyst layer (201a) is formed on the surface of the foundation layer, where the catalyst layer includes a protruding area. A graphene layer (301) is in contact with the protruding area. The protruding area of the catalyst layer is an area corresponding to the boundary of the first and second layers. USE - Semiconductor device. ADVANTAGE - The device utilizes a continuously long graphene layer without breaking an interconnect, so that the long interconnect with low resistance is realized. The device removes mask of a mark area, so that the catalyst layer is formed on the interconnect area and the mark area. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for manufacturing a semiconductor device. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view illustrating a method for manufacturing a semiconductor device. Aggregation layers (101, 102) Catalyst layer (201a) Graphene layer (301) Interlayer insulating film (401) Barrier metal film (402)