• 专利标题:   Ferroelectric field-effect transistor for use as nonvolatile memory elements, comprises substrate, source and drain, channel, gate stack having interfacial layer, and layer of ferroelectric material.
  • 专利号:   WO2022216371-A2, WO2022216371-A3
  • 发明人:   SALAHUDDIN S, TAN A J
  • 专利权人:   UNIV CALIFORNIA
  • 国际专利分类:   H01L000/00, H01L029/00, H01L029/02, H01L029/51
  • 专利详细信息:   WO2022216371-A2 13 Oct 2022 H01L-000/00 202288 Pages: 29 English
  • 申请详细信息:   WO2022216371-A2 WOUS017203 22 Feb 2022
  • 优先权号:   US153180P

▎ 摘  要

NOVELTY - The transistor (10) has a substrate (12). A source (14) mounted over a first region (16) of the substrate. A drain (18) mounted over a second region (20) of the substrate. The second region is spaced apart from the first region. A channel (22) comprised of a semiconductor material within a third region (24) that is between the first region and the second region. A gate stack (26) comprises an interfacial layer (28) mounted over the channel. The interfacial layer has a permittivity that is greater than 3.9. A layer of ferroelectric material (30) mounted over the interfacial layer. The channel comprises crystalline silicon, poly-crystalline silicon, amorphous silicon and oxide semiconductors. The oxide semiconductor comprises indium gallium zinc oxide, indium tungsten oxide and indium oxide. The channel comprises crystalline, poly-crystalline, or amorphous forms of carbon- based semiconductors. The carbon- based semiconductors comprise carbon nanotubes and graphene. USE - Ferroelectric field-effect transistor used as non-volatile memory element within nonvolatile memory integrated circuit (IC). ADVANTAGE - The ferroelectric field-effect transistor (FeFET) has crystalline silicon channels and an endurance exceeding 10 12 cycles. It has very good retention behavior. The high/interfacial layer improves FeFET performance and reliability. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method for fabricating ferroelectric field-effect transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of silicon-on-insulator, gate-first FeFET. 10Ferroelectric field-effect transistor 12Substrate 14Source 16First region 18Drain 20Second region 22Channel 24Third region 26Gate stack 28Interfacial layer 30Ferroelectric material