▎ 摘　　要

NOVELTY - The transistor (11) has a source/drain electrode (210) spaced apart from another source/drain electrode in direction. A channel pattern (300) is provided between the electrodes. A gate electrode (410) is provided on a side surface of the channel pattern, and a gate insulation layer (510) is placed between the pattern and the gate electrode. A graphene insertion layer (710) is formed between the latter electrode and the pattern. A region of a surface of one of the electrodes faces the gate insulation layer in the direction, and the insertion layer extends in another direction between the insulation layer and the former electrode. USE - Vertical channel transistor i.e. vertical channel array transistor, for use in a semiconductor device. ADVANTAGE - The source/drain electrode is provided with the channel pattern, the gate electrode is provided on the side surface of the channel pattern, and the gate insulation layer is provided between the gate pattern and the gate electrode, thus reducing area occupied by each unit device in top view, and reducing manufacturing cost of the transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a vertical channel transistor. 11Vertical channel transistor 100Substrate 210, 220Source/drain electrodes 300Channel pattern 410, 420Gate electrodes 510, 520Gate insulation layers 710, 720Graphene insertion layers