▎ 摘　　要

NOVELTY - The hybrid transistor and memory cell (400) comprises a substrate with a step. A thin conductive material on the substrate extended to an edge to expose an edge of the thin conductive material. A gap is provided in thin conductive material and two-dimensional (2D) semiconductor material formed within the gap connecting thin conductive material sections on either side of the gap. A source electrode contacting the thin conductive material on an opposite side of 2D semiconductor material from the edge of the thin conductive material. A dual function gate dielectric and switching material is provided upon the thin conductive material and 2D semiconductor material. A gate dielectric is provided on the dual function dielectric in alignment with the 2D semiconductor material. The thin conductive material is provided as van der Waals material that includes graphene. The 2D semiconductor material is provided as transition-metal-dichalcogenide material and tungsten-disulphide (WS2). USE - Hybrid transistor and memory cell for helping mimic the workings of human brain with significant gains in computational energy-efficiency. ADVANTAGE - The hybrid cell with unidirectional current pulses that can simplify the array design, and provide easier integration with the transistor for minimizing the static power consumption and improving the robustness of a large-scale crossbar array, significantly reduces the area (and volume) overhead by resulting in increased lateral and vertical integration density. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a hybrid transistor and memory cell. 400Hybrid transistor and memory cell 402Separator transistor 404Memory