• 专利标题:   Vertical variable resistance memory device, has pillar structure for extending in direction through gate electrodes and insulation patterns on substrate, where pillar structure includes variable resistance pattern on sidewall of vertical gate electrode.
  • 专利号:   US2022029095-A1
  • 发明人:   HONG J, LEE K, YOO S, SEO H, KIM Y, KIM H
  • 专利权人:   SAMSUNG ELECTRONICS CO LTD
  • 国际专利分类:   H01L023/00, H01L027/24, H01L045/00
  • 专利详细信息:   US2022029095-A1 27 Jan 2022 H01L-045/00 202222 English
  • 申请详细信息:   US2022029095-A1 US192093 04 Mar 2021
  • 优先权号:   US192093

▎ 摘  要

NOVELTY - The device has gate electrodes (125) spaced apart from each other in a first direction on a substrate (100). Each of the gate electrodes includes graphene and extendes in a second direction, where the first direction being perpendicular to an upper surface of the substrate and the second direction being parallel to the upper surface. Insulation patterns (115) include boron nitride (BN). Pillar structures include a vertical gate electrode and a variable resistance pattern on a sidewall of the vertical electrode, where the pillar structure extendes in direction through the gate electrodes and the insulation patterns on the substrate. The insulation pattern includes hexagonal BN or amorphous BN. USE - Vertical variable resistance memory device. ADVANTAGE - The vertical variable resistance memory device comprises gate electrodes that are spaced apart from each other in a first direction on a substrate, where first direction is perpendicular to an upper surface of the substrate and second direction is substantially parallel to the upper surface, and thus enables to improve the reliability of the memory device. DETAILED DESCRIPTION - (100) Substrate (110) First Insulation Layer First Insulation Layers (115) First Insulation Pattern Second Insulation Patterns, First Insulation Patterns (120) Gate Electrode Layer Gate Electrode Layers (125) Gate Electrode Gate Electrodes, Upper Gate Electrode (130) First Insulating Interlayer Third Insulating Interlayers, Second Insulating Interlayers (140) Hole Holes (150) Variable Resistance Pattern (160) Vertical Electrode Vertical Electrodes (170) Pillar Structure Pillar Structures (180) Second Insulating Interlayer (190) Opening Openings (195) Second Insulation Pattern Second Insulation Patterns (200) First Contact Plug Second Contact Plugs, First Contact Plugs (205) Second Contact Plug Second Contact Plugs (210) Third Insulating Interlayer (220) First Wiring Second Wirings, First Wirings (225) Second Wiring Second Wirings DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a vertical variable resistance memory device. Substrate (100) Insulation patterns (115) Gate electrodes (125) Insulating interlayer (130) Contact plug (200)