▎ 摘　　要

NOVELTY - The method involves providing (S1) a base, and forming (S2) a graphene layer on the upper surface of the substrate. A gate dielectric layer is formed (S3) on the upper surface of the graphene layer. A gate electrode layer is formed (S4) on the upper surface of the gate dielectric layer. A support layer is formed (S5) on the upper surface of the graphene layer. The laminated structure composed of the gate dielectric layer, the gate electrode layer and the support layer is mechanically peeled (S6) from the surface of the graphene layer. The stacked structure is transferred (S7) to a target substrate. The support layer is removed (S8), and the top gate structure composed of the gate dielectric layer and the gate electrode layer is left on the surface of the target substrate. USE - Method for preparing top gate structure for semiconductor structure (claimed) used in semiconductor integrated circuit. ADVANTAGE - The method enables realizing stripping of any top gate structure, transferring to any target substrate to form Van der Waals, reducing damage of the top gate structure manufacturing process to the target substrate material, improving device performance and reducing manufacturing cost of the top gate structure. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a semiconductor structure. DESCRIPTION OF DRAWING(S) - The drawing shows a flow chart illustrating a method for preparing a top gate structure. (Drawing includes non-English language text) Step for providing a base (S1) Step for forming a graphene layer on the upper surface of the substrate (S2) Step for forming a gate dielectric layer on the upper surface of the graphene layer (S3) Step for forming a gate electrode layer on the upper surface of the gate dielectric layer (S4) Step for forming a support layer on the upper surface of the graphene layer (S5) Step for mechanically peeling the laminated structure (S6) Step for transferring the stacked structure to a target substrate (S7) Step for removing the support layer (S8)