• 专利标题:   Method for manufacturing semiconductor device, involves forming grid medium layer between graphene-containing layer and exposed seed layer using photo resist as mask and forming gate metal on gate dielectric medium to remove photo-resist.
  • 专利号:   CN103295912-A, WO2014187022-A1, CN103295912-B, US2015364567-A1, US9349825-B2
  • 发明人:   WEI C, LI J, LIU Q, FENG Z, WANG J, HE Z
  • 专利权人:   CHINA ELECTRONICS TECHNOLOGY GROUP CORP, 13TH RES INST CHINA ELECTRONIC SCI TEC, FENG Z, LI J, WEI C, LIU Q, HE Z, WANG J
  • 国际专利分类:   H01L021/28, H01L021/336, H01L021/31, H01L021/331, H01L029/16, H01L029/66, H01L029/423, H01L029/778
  • 专利详细信息:   CN103295912-A 11 Sep 2013 H01L-021/336 201428 Pages: 16 Chinese
  • 申请详细信息:   CN103295912-A CN10189470 21 May 2013
  • 优先权号:   CN10189470

▎ 摘  要

NOVELTY - The method involves providing graphene containing layer (4) on a substrate (1) and depositing metal layer (5) on graphene-containing layer. The exposed graphite is etched to remove exposed metal using photo-resist pattern as a mask. A gate mask pattern (11) is formed between source electrode (7) and drain electrode (9) using photo-resist. A grid medium layer is formed between graphene-containing layer and exposed seed layer (12) using photo resist to form gate pattern as mask. The gate metal is formed on the gate dielectric medium (13) to remove the photo-resist. USE - Method for manufacturing semiconductor device based on self-aligned graphene transistor technology. ADVANTAGE - The seed layer is formed on the surface of graphite alkene to expose out to form gate dielectric on the seed layer, and then gate metal is formed on the gate dielectric to form graphene transistor, so that the distance between the gate source and gate drain can be reduced. Hence the performance of the grapheme transistor can be improved. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram illustrating the process for manufacturing semiconductor device based on self-aligned graphene transistor technology. Substrate (1) Graphene containing layer (4) Metal layer (5) Source electrode (7) Drain electrode (8) Gate mask pattern (11) Seed layer (12) Gate dielectric medium (13)