▎ 摘　　要

NOVELTY - The method involves forming a channel structure on a substrate (12), where the channel structure comprises first semiconductor layers and second semiconductor layers (22) alternately disposed over one another. A gate structure is formed on the channel structure. A source/drain structure (40) is formed adjacent to the gate structure, where the source/drain structure comprises graphene. The gate structure is removed to form a first recess. The first semiconductor layers is removed to form a second recess between the second semiconductor layers. A work function metal layer (50) is formed in the first recess and the second recess. An interlayer dielectric (ILD) layer (60) is formed around the gate structure. USE - Method for fabricating a nanowire transistor using graphene as source/drain structure and/or contact plug in a semiconductor industry. ADVANTAGE - The method enables improving control of gate to channel by using high-k dielectric layers, and reducing leakage current that causes increase of off-state power consumption, and consequently causes functionality failure due to severe short channel effects and thin gate dielectrics when transistor shrink into or below 30 nm regime. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a nanowire transistor. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of a nanowire transistor. Substrate (12) Semiconductor layer (22) Source/drain structure (40) Work function metal layer (50) ILD layer (60)