• 专利标题:   Packaged semiconductor used in electronic device, has metal layer which is arranged on surface of substrate that is graphene plate which is made of graphene material and chip is fixed on substrate through graphite-based die bonding material.
  • 专利号:   CN111640710-A
  • 发明人:   WANG X, TANG H
  • 专利权人:   GREAT TEAM BACKEND FOUNDRY DONGGUAN CO
  • 国际专利分类:   H01L021/52, H01L021/56, H01L023/31, H01L023/367, H01L023/373, H01L023/492
  • 专利详细信息:   CN111640710-A 08 Sep 2020 H01L-023/367 202078 Pages: 9 Chinese
  • 申请详细信息:   CN111640710-A CN10432268 21 May 2020
  • 优先权号:   CN10432268

▎ 摘  要

NOVELTY - The packaged semiconductor has a substrate (100) and a chip (200) that are arranged on the substrate. The substrate comprises the substrate and a metal layer (120) is arranged on a surface of the substrate. The substrate is a graphene plate (110) which is made of a graphene material. The chip is fixed on the substrate through a graphite-based die bonding material (700). The graphite-based die attach material is graphite, a mixture of graphite and silver or a mixture of graphene and copper. The metal layer comprises a first surface plating layer and a second surface plating layer that are respectively located on two side surfaces of the graphene plate. USE - Packaged semiconductor used in electronic device (claimed). ADVANTAGE - The graphene is used as a material of the substrate, in order to achieve effective heat dissipation of a semiconductor product, by utilizing excellent heat dissipation performance of the graphene and the graphene is applied to high-power devices to guarantee normal use temperature. The chip is fixed by the graphene-based die bonding material, so that heat of the chip is better transferred to the substrate and the heat dissipation effect is improved. The metal level is utilized to carry out routing, while wiring way or weld with welding material. The scheme has good heat dissipation performance, improves the brittleness of the product and avoids cracking. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a semiconductor packaging method. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a packaged semiconductor structure. Substrate (100) Graphene plate (110) Metal layer (120) Chip (200) Graphite-based die bonding material (700)