▎ 摘　　要

NOVELTY - The method involves forming an insulator (110). A dielectric layer is deposited over a gate (115) and an insulator. A channel is formed with a bilayer graphene layer formed on the dielectric layer, where the dielectric layer provides a flat surface on which the channel is formed. Another dielectric layer is deposited over the bilayer graphene layer. A local gate is formed over the latter dielectric layer, where local gates are capacitively coupled to the channel of the bilayer graphene layer. The local gates form gates to control a portion of the bilayer graphene layer. USE - Method for forming an electronic device e.g. FET, electron conduction type device and hole conduction type device. ADVANTAGE - The method enables forming a bilayer graphene layer device with patterned top and bottom gates to bias different voltages on different devices on a same wafer to different band gap in an effective manner. The method enables reducing gate leakage problem, and patterning the top and bottom gates. The method enables selecting angle, dose and energy of the ion implantation to provide high conductivity to source and drain regions to minimize source and drain resistance of a transistor to be formed in an effective manner. DESCRIPTION OF DRAWING(S) - The drawing shows a top-down view of an electronic device. Substrate (105) Insulator (110) Local gates (115, 140, 155-170) Contacts (145) Transistors (175-185)