• 专利标题:   Integrated circuit structure for use in computing device, has graphene layer including first side coupled to conductor, and second side perpendicular to first side, and two-dimensional transition metal dichalcogenide layer coupled to base.
  • 专利号:   EP4156299-A1, US2023102695-A1, KR2023043689-A, CN115863308-A
  • 发明人:   NAYLOR C, MAXEY K, OBRIEN K, DOROW C, LEE S, PENUMATCHA A V, AVCI U E, METZ M, CLENDENNING S B, METZ M V, OBRIEN K P, NAYLOR C H, KIRBY M, CHELSEA D, RISUDARAT, VERMA P A, ABSIYUGARI, BEE C S, ARFCHI U E
  • 专利权人:   INTEL CORP, INTEL CORP, INTEL CORP
  • 国际专利分类:   H01L029/267, H01L029/778, H01L029/786, H01L027/088, H01L029/417, H01L029/45, H01L023/522, H01L023/528, H01L023/532
  • 专利详细信息:   EP4156299-A1 29 Mar 2023 H01L-029/778 202327 Pages: 15 English
  • 申请详细信息:   EP4156299-A1 EP197316 23 Sep 2022
  • 优先权号:   US485301

▎ 摘  要

NOVELTY - The structure has a base (102) comprising silicon dioxide (SiO2). A conductor (104) comprises copper extending through a portion of the base. A barrier (108) is formed between the base and the conductor. A graphene layer (112) includes a first side coupled to the conductor, and a second side perpendicular to the first side. A two-dimensional (2D) transition metal dichalcogenide (TMD) layer is coupled to the base and the second side of the graphene layer, where the 2D TMD layer comprises molybdenum disulfide, tungsten disulfide, molybdenum diselenide, tungsten diselenide, indium monoselenide, molybdenum telluride or tungsten telluride, the barrier comprises tantalum nitride or tantalum manganese dioxide. USE - Integrated circuit structure for use in a computing device. Uses include but are not limited to a laptop, a netbook, a notebook, a set-top box, a smartphone, a tablet, a personal digital assistant (PDA), a mobile phone, a desktop computer and a server. ADVANTAGE - The structure enables scaling to smaller and smaller features to increase densities of functional units on limited real estate of semiconductor chips and shrink transistor size to allow for incorporation of an increased number of memory or logic devices on a chip, thus lending to the fabrication of products with increased capacity and optimizing the performance of each device to be increased significantly. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a method for fabricating an integrated circuit structure. DESCRIPTION OF DRAWING(S) - The drawing shows a cross sectional view of a graphene contact. 102Base 104Conductor 108Barrier 112Graphene layer