▎ 摘　　要

NOVELTY - The method involves depositing a semiconductor layer (101) on the substrate, and forming a gate dielectric layer (103), a gate electrode (104), a sidewall spacer (105) and a main gate electrode (106) on the semiconductor layer gate structure. A metal film is deposited on the gate structure as the source and drain contact metal layer (107) of the thin film transistor, and a certain thickness of metal film is left on the sidewall and the main gate electrode. An interlayer dielectric layer is deposited on the source and drain contact metal layer. The photoresist is used as a mask, a window is opened to define the total pattern size of the source and drain regions and the gate, and the rest of the interlayer dielectric layer is etched away. The remaining interlayer dielectric layer is used as a mask to etch away the exposed metal layer. The remaining interlayer dielectric layer is served as a self-aligned mask to protect the contact area from being etched. USE - Self-aligned patterning method for source and drain contact metals of undoped thin film transistors. ADVANTAGE - The method realizes that the excess metal on the sidewall and the top of the gate is etched away and protects the source and drain regions. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic diagram illustrating the exposed contact metal film using the remaining dielectric layer as a self-aligned mask. Semiconductor layer (101) Gate dielectric layer (103) Gate electrode (104) Sidewall spacer (105) Main gate electrode (106) Source and drain contact metal layer (107)