▎ 摘　　要

NOVELTY - Semiconductor package (100) comprises (i) a first microelectronic device and a second microelectronic device on a package substrate (102), where the first microelectronic device has a top surface that is substantially coplanar to a top surface of the second microelectronic device; a third microelectronic device on the package substrate, where the third microelectronic device has a top surface positioned above the top surfaces of the first and second microelectronic devices; a first conductive layer (122a) on the first and second microelectronic devices; a second conductive layer (122b) on the third microelectronic device, where the second conductive layer has a top surface that is substantially coplanar to a top surface of the first conductive layer; and a first thermal interface material (TIM) on the first conductive layer, and a second TIM on the second conductive layer. USE - The semiconductor package is useful in 3d buildup of thermally conductive layers to resolve die height differences. ADVANTAGE - The semiconductor package provide improvements to existing packaging by substantially increasing the overall thermal conductivity and improvements to existing packaging solutions by implementing (or disposing/covering) the first conductive layer directly over the entire footprint (or top surface area) of the first and second devices to substantially reduce the formation (or possibility) of hotspots and improves existing technologies by implementing the first and second conductive layers (or the first, second, and third conductive layers) with different thicknesses directly on the top surfaces of the devices to substantially remove (or minimize) any device thickness variations. DETAILED DESCRIPTION - Semiconductor package (100) comprises (i) a first microelectronic device and a second microelectronic device on a package substrate (102), where the first microelectronic device has a top surface that is substantially coplanar to a top surface of the second microelectronic device; a third microelectronic device on the package substrate, where the third microelectronic device has a top surface positioned above the top surfaces of the first and second microelectronic devices; a first conductive layer (122a) on the first and second microelectronic devices; a second conductive layer (122b) on the third microelectronic device, where the second conductive layer has a thickness that is less than a thickness of the first conductive layer, and where the second conductive layer has a top surface that is substantially coplanar to a top surface of the first conductive layer; and a first thermal interface material (TIM) on the first conductive layer, and a second TIM on the second conductive layer or (ii) the first microelectronic device and the second microelectronic device on the package substrate, where the first microelectronic device has a top surface that is substantially coplanar to a top surface of the second microelectronic device; the third microelectronic device on the package substrate; a first conductive layer on the first and second microelectronic devices; a second conductive layer on the third microelectronic device, where the second conductive layer has a thickness that is different than a thickness of the first conductive layer, and where the second conductive layer has a top surface that is substantially coplanar to a top surface of the first conductive layer; a first TIM on the first conductive layer, and a second TIM on the second conductive layer, where the first TIM has a thickness that is substantially equal to a thickness of the second TIM; an integrated heat spreader (IHS) (120) on the first and second TIMs; and conductive slugs coupled to a periphery region of a bottom surface of the first conductive layer. An INDEPENDENT CLAIM is included for a method to form the semiconductor package. DESCRIPTION OF DRAWING(S) - The drawing shows a cross-sectional view of semiconductor package with the IHS, the TIM, the first conductive layer, the second conductive layer, microelectronic devices, and the package substrate with bridges. Semiconductor package (100) Package substrate (102) Integrated heat spreader (120) First conductive layer (122a) Second conductive layer (122b)