▎ 摘　　要

NOVELTY - The G-FET (10) has comprising a negative differential resistance (NDR) region that comprises a zero-bandgap graphene layer (16) placed on a back-gate. A top-gate (18) is placed on a portion of the graphene layer. A source (20) is placed on a portion of the graphene layer and adjacent to the top-gate. A drain (22) is placed on a portion of the graphene layer adjacent to the top-gate and displaced from the source. The graphene layer operates in the NDR region when source-drain voltage and top-gate voltage are simultaneously swept across a dirac point. USE - Dual-gate G-FET for use in a graphene-based pattern matching circuit (claimed), for non-Boolean computational architectures. ADVANTAGE - The G-FET is fabricated using pristine single layer and bilayer graphene so as to preserve graphene's inherent physical properties of high electron mobility, exceptional heat conduction properties, high saturation velocity, convenient planar geometry and compatibility for integration with commonly used integrated circuit substrates. The G-FET can fix back-gate voltage at different voltage, and keeps the source-drain voltage and top-gate voltage sweep setting, so that strength of an NDR effect can be tuned, thus providing additional degree of freedom for logic circuit design by controlling NDR with back-gate voltage. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for a graphene-based pattern matching circuit. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a scanning electron microscope image of a graphene-based dual-gate transistor having a negative differential resistance region. Dual-gate G-FET (10) Zero-bandgap graphene layer (16) Top-gate (18) Source (20) Drain (22)