• 专利标题:   Method for forming interconnect structure involves etching lithographic patterning structure to form partially patterned structure having first conductive lines and to expose top surface of first etch stop layer, etching first etch stop layer of patterned structure, and forming self-aligned via.
  • 专利号:   US2023045689-A1
  • 发明人:   NAIK M, HWANG H D, LANG C, REN H, LU C, JIANG H
  • 专利权人:   APPLIED MATERIALS INC
  • 国际专利分类:   H01L021/027, H01L021/306, H01L021/3213, H01L021/768
  • 专利详细信息:   US2023045689-A1 09 Feb 2023 H01L-021/768 202314 English
  • 申请详细信息:   US2023045689-A1 US968201 18 Oct 2022
  • 优先权号:   US662200, US968201

▎ 摘  要

NOVELTY - Method for forming interconnect structure involves etching a lithographic patterning structure to form a partially patterned structure having first conductive lines (202) and to expose a top surface of a first etch stop layer (210), etching the first etch stop layer of the patterned structure to form second conductive lines (212) and expose a top surface of a barrier layer (106), and forming self-aligned via. USE - Method for forming interconnect structure used for semiconductor device. ADVANTAGE - The method has high etch rate metal etch to etch top metal layer to minimize hard mask sputtering. DESCRIPTION OF DRAWING(S) - The drawing shows an isometric view of the interconnect structure. 102Substrate 106Barrier layer 202First conductive lines 210First etch stop layer 212Second conductive lines