▎ 摘　　要

NOVELTY - The method involves forming an opening through a dielectric layer and an underlying etching stop layer to expose a metal line. A graphene layer is catalytically grown on an exposed surface of the metal line. An amorphous carbon layer is deposited on sidewalls of the opening, where the steps of catalytically growing the graphene layer and depositing the amorphous carbon layer are performed simultaneously. A portion of the amorphous carbon layer is arranged laterally adjacent to the graphene layer and the etching stop layer. USE - Method of manufacturing device, such as, transistor, capacitor, resistor, in integrated circuit (IC) fabrication. ADVANTAGE - One or more metal layers are formed over the individual devices to provide connections between the individual devices and to provide connections to external devices. The back end of line (BEOL) is the second portion of IC fabrication where the individual devices get interconnected with wiring or metal layers on the wafer. The barrier layers are used to prevent diffusion of the conductor materials of the metal layers, such as, the aluminum or Cu, into the adjacent areas of the IC. The final passivation layer is used for protecting the IC from mechanical abrasion during probe and packaging and to provide a barrier to contaminants. DESCRIPTION OF DRAWING(S) - The drawing shows a cross sectional view various metal layers formed on individual devices of an IC. Substrate (130) Inter-metal dielectric layers (133) Metal layer (141) Second metal layer (143) Additional metal layers (145)