• 专利标题:   Semiconductor devices with improved electrical characteristics e.g. integrated circuits including metal-oxide-semiconductor field effect transistors, has substrate, first interlayer insulating layer on substrate, lower interconnection line in first insulating layer, and upper interconnection line.
  • 专利号:   US2023064127-A1
  • 发明人:   JUNG E, YOO S, KIM R, KIM K, LEE J
  • 专利权人:   SAMSUNG ELECTRONICS CO LTD
  • 国际专利分类:   H01L023/522, H01L023/532, H01L029/45
  • 专利详细信息:   US2023064127-A1 02 Mar 2023 H01L-023/522 202321 English
  • 申请详细信息:   US2023064127-A1 US053487 08 Nov 2022
  • 优先权号:   KR106870

▎ 摘  要

NOVELTY - Semiconductor device has a substrate, a first interlayer insulating layer (110) on the substrate, a lower interconnection line in the first interlayer insulating layer, etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer (120) on etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through etch stop layer and contacting the lower interconnection line. The via portion comprises a barrier pattern and a conductive pattern on the barrier pattern. The barrier pattern comprises a first portion that is in the conductive pattern and the second interlayer insulating layer and a second portion in the conductive pattern and the lower interconnection line. The first portion of the barrier pattern has a first nitrogen concentration. The second portion of the barrier pattern has a second nitrogen concentration. USE - Semiconductor devices with improved electrical characteristics e.g. integrated circuits including metal-oxide-semiconductor field effect transistors (MOSFETs). ADVANTAGE - The device improves electrical characteristics, performance of the active contact and reliability of the device, reduces the electrical resistivity of the lower interconnection line and manufacturing cost, simplifies the manufacturing process, and prevents the damage of first barrier layer and/or the conductive pattern. DETAILED DESCRIPTION - Semiconductor device has a substrate, a first interlayer insulating layer on the substrate, a lower interconnection line in the first interlayer insulating layer, etch stop layer on the first interlayer insulating layer and the lower interconnection line, a second interlayer insulating layer on etch stop layer, and an upper interconnection line in the second interlayer insulating layer. The upper interconnection line includes a via portion extending through etch stop layer and contacting the lower interconnection line. The via portion comprises a barrier pattern and a conductive pattern on the barrier pattern. The barrier pattern comprises a first portion that is in the conductive pattern and the second interlayer insulating layer and a second portion in the conductive pattern and the lower interconnection line. The first portion of the barrier pattern has a first nitrogen concentration. The second portion of the barrier pattern has a second nitrogen concentration. The first nitrogen concentration is greater than the second nitrogen concentration. The first portion of the barrier pattern has a first thickness. The second portion of the barrier pattern has a second thickness. The first thickness is greater than the second thickness. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of semiconductor devices. 110First interlayer insulating layer 120Second interlayer insulating layer BM2Second barrier pattern W1First width W2Second width