▎ 摘　　要

NOVELTY - The graphene transistor device has a gate structure (1202) with a dielectric sidewall spacer (1106) that is disposed between source and drain electrodes (1206), and a graphene layer adjacent to at least one of the source and drain electrodes. An interface between the at least one of source and drain electrodes and graphene layer maintains a consistent degree of contact throughout the interface. The gate structure has a gate electrode that includes a recessed portion. USE - Graphene transistor device for graphene transistor system (claimed). ADVANTAGE - Prevents undercutting of the gate dielectric by not employing chemical etching. Allows for good electrical contact to be made since source/drain regions of the graphene are also left completely exposed. The devices formed are immediately scalable and can be integrated with relative ease by utilizing lift-off lithographic processing techniques to fabricate the gate electrode. The parasitic resistances and capacitances are minimized by self-aligned gating, thus enhances the performance of the device for high-speed or high-frequency electronics. Prevents increase in contact resistance caused by inconsistent contact between the graphene and source/drain electrodes since interface maintains consistent degree of contact throughout the interface as well as consistent degree of electrical conductivity between the graphene layer and source and drain electrodes throughout the interface. DESCRIPTION OF DRAWING(S) - The drawing shows a perspective view of the graphene field effect transistor (GFET) device structure during fabrication illustrating deposition of source and drain electrodes. Seed layer (802) Dielectric sidewall spacer (1106) Gate structure (1202) Gate electrode (1204) Source and drain electrodes (1206)