• 专利标题:   Interconnect structure used to fabricate e.g. transistors comprises first contact feature in first dielectric layer, second dielectric layer, second contact feature over first contact feature, barrier layer between second dielectric layer and second contact feature and carbon layer.
  • 专利号:   US2021057335-A1, CN112420664-A, TW202109754-A, US11114374-B2
  • 发明人:   YANG S, LUO G, CHUNG C, LEE M, SHUE S, LI M, SUI X, LEE M H
  • 专利权人:   TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MFG CO LTD, TAIWAN SEMICONDUCTOR MFG CO LTD
  • 国际专利分类:   H01L021/768, H01L023/522, H01L023/528, H01L023/532, H01L021/76, H01L023/52
  • 专利详细信息:   US2021057335-A1 25 Feb 2021 H01L-023/522 202132 English
  • 申请详细信息:   US2021057335-A1 US547847 22 Aug 2019
  • 优先权号:   US547847

▎ 摘  要

NOVELTY - Interconnect structure (200) comprises: first contact feature in first dielectric layer (210); second dielectric layer (220) over first dielectric layer; second contact feature over first contact feature; barrier layer between second dielectric layer and second contact feature; and carbon layer disposed between second and first contact features, where the carbon layer is in contact with second contact feature. The carbon layer comprises graphene layer. The barrier layer comprises cobalt-tungsten alloy, cobalt-manganese alloy, copper-aluminum alloy and/or nickel-aluminum alloy. The barrier layer comprises titanium nitride, tantalum nitride, cobalt nitride, tungsten nitride and/or ruthenium nitride. The structure further comprises catalytic metal layer disposed between carbon layer and first contact feature. The catalytic metal layer comprises nickel, cobalt, copper, ruthenium, rhenium, rhodium, palladium, iridium, platinum or gold. USE - The structures are useful for fabricating integrated circuit (IC) devices e.g. transistors and semiconductor device. ADVANTAGE - The structures: involves the capping layer that can include a material that prevents or eliminates diffusion and/or reaction of constituents between the gate dielectric and other layers of the gate electrode; and significantly delay (and, in some situations, prevent) signals from being routed efficiently to and from IC devices e.g. transistors, negating any improvements in performance of such IC devices in the advanced technology nodes. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is also included for contact structure. DESCRIPTION OF DRAWING(S) - The figure shows a fragmentary cross-sectional view the back-end-of-line interconnect structure of the semiconductor device at various stages of fabrication. Semiconductor device (20) Substrate (22) Interconnect structure (200) First dielectric layer (210) Metal fill layer (216) Second dielectric layer (220)