▎ 摘　　要

NOVELTY - The sensor has a photoelectric Monte memristor array (1), a storage layer (2), and a logic circuit layer (3) are respectively established on the three stacked chips. The chip is connected with a metal connecting column (4) and is connected with metal-metal connecting column. The photoelectric Monte memristor array is located on the uppermost layer of the chip. The storage layer is located below the photoelectric Monte memristor array. The logic circuit layer comprises a square wave shaping circuit, a digital frequency meter time-to-digital converter (TDC), and a control unit circuit. The square wave shaping circuit and the digital frequency meter TDC are used for filtering, shaping, and quantizing a pulse signal from a Monte memristor. The control unit circuit includes a logic circuit for controlling the reading and writing of the storage unit. USE - High-speed three-dimensional (3D) stacked image sensor used in various fields e.g. military, medical treatment, security and industry fields. ADVANTAGE - The sensor realizes the integration of optical signal perception and signal conversion, and solves the problem of chip lead interconnection that cannot be overcome by traditional (digital-to-analog conversion) AD. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of the high-speed three-dimensional (3D) stacked image sensor (Drawing includes non-English language text). 1Photoelectric Monte memristor array 2Storage layer 3Logic circuit layer 4Metal connecting column