1. 平台首页
  2. 国际专利信息
  • 专利标题:   Apparatus for voltage equalization for pillars of memory array, comprises access line, conductive pillar having first end configured for coupling with access line, conductive pillar having second end opposite first end of conductive pillar, memory cell coupled between conductive pillar and word line.
  • 专利号:   US2022180926-A1, WO2022126065-A1, TW202228134-A, US11437097-B2, TW785915-B1
  • 发明人:   FANTINI P, BEDESCHI F, VILLA C
  • 专利权人:   MICRON TECHNOLOGY INC, MICRON TECHNOLOGY INC
  • 国际专利分类:   G11C013/00, H01L045/00, G11C016/04, G11C016/30, H01L027/11573, G11C008/08
  • 专利详细信息:   US2022180926-A1 09 Jun 2022 G11C-013/00 202251 English
  • 申请详细信息:   US2022180926-A1 US116893 09 Dec 2020
  • 优先权号:   US116893

▎ 摘　　要

NOVELTY - Apparatus comprises an access line, a conductive pillar having a first end configured for coupling with the access line, and the conductive pillar having a second end opposite the first end of the conductive pillar, a memory cell (105) coupled between the conductive pillar and a word line, and a layer adjacent to the second end of the conductive pillar. The layer is configured to support an equalization of voltage between the conductive pillar and a ground node. The row decoder (120), column decoder (125), and sense component (130) may be co-located with the local memory controller (160). USE - Apparatus for voltage equalization for pillars of NAND flash memory array word line circuit. ADVANTAGE - The memory array may be configured to support a dissipation or equalization of charge or voltage of structures that are floated during operation of a memory array. DETAILED DESCRIPTION - An INDEPENDENT CLAIM is included for a method for voltage equalization for pillars of a memory array, which involves: (a) forming an access line extending along a first direction; (b) forming a memory cell coupled between a conductive pillar and a word line; (c) forming the conductive pillar extending along a second direction, orthogonal to the first direction, the conductive pillar having a first end for coupling with the access line, and the conductive pillar having a second end opposite the first end of the conductive pillar along the second direction; (d) forming a first layer in contact with the second end of the conductive pillar; and (e) forming a second layer adjacent to the first layer and opposite to the conductive pillar along the second direction, where the first layer is configured for dissipating a voltage difference between the conductive pillar and the second layer. DESCRIPTION OF DRAWING(S) - The drawing shows a schematic view of a memory array that supports voltage equalization for pillars of a memory array. Memory cell (105) Row decoder (120) Column decoder (125) Sense component (130) Local memory controller (160)