国家/地区
IPC部
IPC大类
IPC小类
IPC
发明人 MOON J（2）
公开年 2023（2）
申请年
专利权人

Method for manufacturing pellicle, involves forming upper silicon nitride layer on upper surface of wafer substrate, where pattern is formed on lower silicon n-nitride layer, and metal layer is formed in lower silicon nitride layer.

MOON S I, KWON Y, WOOK Y B, MOON J, KIM K S, LEE S M

Field effect transistor comprises substrate, and passivation layer on substrate providing passivated substrate, which is on top, bottom and sides of substrate, and graphene lateral heterostructure field effect transistor (LHFET) on passivated substrate.

SEO H C, MOON J, SON K