国家/地区
IPC部 H（2）
IPC大类 H01（2）
IPC小类 H01L（2）
IPC
发明人 PU H（2）
公开年
申请年 2020（2）
专利权人

Memory device has multiple stacked tiers having redistribution structure closest to first semiconductor die comprising thermally conductive layer connected to first semiconductor die, and second semiconductor dies wrapped by encapsulant.

HSIEH Y, CHIANG Y, KO T, LIU M, PU H, HUANG C

Preparing flexible graphite-based silicon nanowire heterojunction comprises e.g. covering graphene substrate with 2 nm thick gold on CVD furnace and turn on the mechanical pump to evacuate.

LI L, ZANG Y, CHEN H, HU J, LIN S, ZHANG G, PU H, FENG X, SONG L, TU Z, LI Z, XU Y, WANG R