国家/地区 台湾（2）
IPC部 H（2）
IPC大类 H01（2）
IPC小类 H01L（2）
IPC H01L021/3205（2）
发明人 REN H（2）
公开年 2021（2）
申请年
专利权人

Forming interconnect structure, comprises e.g. etching patterned interconnect stack and first etch stop layer to form first conductive lines and second conductive lines and expose top surface of first etch stop layer and barrier layer.

JIANG H, LU C, REN H, LANG C, HWANG H D, NAIK M

Planar transistor device in electronics industry, has layer of two-dimensional (2D) material whose planar top surface and planar bottom surface that are arranged parallel to planar surface of semiconductor substrate.

PRITCHARD D, YANG H, REN H, NAYYAR N, PRABHU M, STREHLOW E, CIMINO S