国家/地区 美国（3） 日本（2）
IPC部 H（3）
IPC大类 H01（3）
IPC小类 H01L（3）
IPC H01L021/768（3） H01L021/3205（2） H01L023/52（2）
H01L023/522（2） H01L023/532（2）
发明人 WADA M（3）
公开年 2015（3）
申请年 2014（3）
专利权人 TOSHIBA KK（3）

Semiconductor device, has catalyst layer which is formed on or in substrate along with interconnect pattern, and graphene layers formed on catalyst layer and arranged in parallel in narrower line width than width of interconnect pattern.

SAITO T, WADA M, ISOBAYASHI A, KAJITA A, SAKAI T

Semiconductor device, has carbon nanotubes that are formed so that graphene layers are stacked in state in which are inclined depthwise with respect to groove and are doped with one element from sidewalls of carbon nanotubes.

SAITO T, WADA M, ISOBAYASHI A, KAJITA A, MIYAZAKI H, SAKAI T

Method for manufacturing semiconductor device, involves sticking graphene layer on substrate with semiconductor elements and forming grapheme wires by processing graphene layer into wiring pattern.

WADA M, KAJITA A, ISOBAYASHI A, SAITO T