国家/地区 美国（4）
IPC部 C（4） H（3）
IPC大类 C01（4） C23（4） H01（3）
IPC小类 C01B（4）
IPC C23C016/455（4）
发明人
公开年 2022（2） 2023（2）
申请年 2022（4）
专利权人

Graphene interconnect structure useful for electronic device comprises first oxide dielectric layer including porous silicon oxide, or amorphous boron nitride, second oxide dielectric layer including aluminum oxide and graphene layer.

KIM C, BYUN K E, SHIN K W, LEE C S, BAEKWON P, PARK B, LEE C, SHIN K, BYUN K

Processing semiconductor for producing high quality devices and structures, involves delivering carbon-containing precursor and hydrogen-containing precursor to processing region of semiconductor processing chamber, forming layer of graphene on substrate positioned in processing region of chamber.

INGLE N K, MALLICK A B, SINGHA R S, WANG J

Preparing nanoparticles on a substrate for composite, involves depositing micro-sized particles or salt precursors on a substrate, and applying a rapid, high temperature thermal shock to the substrate and the micro-sized particles or the salt precursors.

YAO Y, CHEN Y, HU L

Plasma enhanced chemical vapor deposition method used in semiconductor structure, comprises turning on radio frequency source of radio frequency system to decompose aromatic hydrocarbon precursor into multiple active radicals at specific frequency to form graphene layer on magnetic layer.

WU Z, NI I, XU Y, HUANG J, WU C, HSU Y, HUANG J Z, HSU Y H