国家/地区 美国（4） 台湾（2） 世界知识产权组织（2）
IPC部 H（4） B（3）
IPC大类 H01（4） B82（2）
IPC小类 H01L（4） B82Y（2）
IPC H01L021/336（4） B82Y040/00（2） H01L021/28（2）
H01L029/16（2） H01L029/78（2）
发明人 AVOURIS P（4）
公开年 2012（4）
申请年 2012（2） 
专利权人 INT BUSINESS.（4）

Formation of transistor structure involves forming graphene layer on insulating layer, forming stack of primary and secondary metal portions, and laterally offsetting sidewalls of primary metal portion relative to secondary portion.

AVOURIS P, FARMER D B, LIN Y, ZHU Y

Semiconductor structure of semiconductor device e.g. MOSFET used in electronic device e.g. personal computer, has nitride layer which is formed on graphene layer between source electrode and drain electrode.

AVOURIS P, NEUMAYER D, ZHU W, NEUMAYER D A

Three-dimensional integrated circuit for three-dimensional hybrid integration of e.g. graphene field-effect transistors comprises semiconductor device, insulator formed on the semiconductor device, interconnect, and graphene device.

AVOURIS P, WU Y, ZHU W, CHANG J B, HAENSCH W E, LIU F, LIU Z

Graphene-based field effect transistor for high-frequency electronics, comprises graphene layer located on insulating layer, first and second metal portions, first and second electrodes, gate dielectric layer, and dielectric seed layer.

AVOURIS P, FARMER D B, LIN Y, ZHU Y, LIN Y M