国家/地区 美国（3） 中国（2）
IPC部 H（4） B（3）
IPC大类 H01（4） B82（3）
IPC小类 H01L（4） B82Y（3）
IPC B82Y040/00（2） B82Y099/00（2） H01L021/336（2）
H01L027/088（2） H01L029/78（2）
发明人 LIU F（5）
公开年 2012（5）
申请年 2012（4） 
专利权人 INT BUSINESS.（3）

Three-dimensional integrated circuit has gate stack portion including graphene layer, disposed on dielectric layer formed on another dielectric layer disposed on source region, drain region, another stack portion and substrate.

CHANG J B, HAENSCH W E, LIU F, LIU Z

Preparing graphene oxide/nano-precious metal composite material, comprises e.g. reducing salt of precious metal using liquid phase reduction method to obtain noble metal solution and dispersing graphene oxide into alcohol solution.

CHENG Y, GUO J, LIU F, SUN A, WANG B, XU G, QIAN Z

Tunnelling field effect transistor structure source region which is made of graphite nano-belt whose width is greater than width of graphene nanometre belt of channel region and drain region.

DU G, LIU F, LIU X, WANG Y

Three-dimensional integrated circuit for three-dimensional hybrid integration of e.g. graphene field-effect transistors comprises semiconductor device, insulator formed on the semiconductor device, interconnect, and graphene device.

AVOURIS P, WU Y, ZHU W, CHANG J B, HAENSCH W E, LIU F, LIU Z

Three-dimensional integrated circuit i.e. hybrid integrated circuit, forming method, involves forming dielectric layer on graphene layer, and forming metallic gate material on dielectric layer.

CHANG J B, HAENSCH W E, LIU F, LIU Z